Lead Design Verification Engineer

What You'll Do

• Create robust verification architecture, verification testplan and verification metric closure documentation to comply with NXP verification and validation process.
• Architect and develop testbenches using SystemVerilog and UVM for functional and power aware RTL verification.
• Contribute to defining verification strategy (Directed, Constrained random and Formal) for IP, Sub-System and SoC verification.
• Develop UVM components like Agents (active and passive), Scoreboards and Environment etc., Develop Assertions, functional coverage.
• Develop Test plan, UVM based test sequences, layered sequences, virtual sequencers.
• Drive closure of verification metrics to cover verification space.
• Work with a team to identify and close gaps in Functional, Power aware and Gate level timing Simulation.
• Develop ‘C’ testcases for HW-FW Simulation and FPGA Prototyping.
• Regression setup, debug of RTL and Gate level Netlist.
• Work closely with Architecture, digital and analog design, DV and validation teams to ensure timely delivery of quality products Minimum Required Qualifications B.S./M.S.
• Electrical/Computer Engineering (or similar degrees) 8+ Years of proven track record of ASIC/SoC verification, taking several chips from specification to tape out.
• Proven Expertise with UVM and/or SystemVerilog based verification.
• Proven experience of standard ASIC verification including Planning Test Testbench creation.
• Code and Functional Coverage Directed and Constrained random stimulus generation and test.
• Low power verification.
• C/C++, Perl, Python scripting.
• Experience working with tools like GIT, Jira, Confluence.
• More information about NXP in India... #LI-7013