2026 Campus - SoC DFT Engineer

What You'll Do

• Participate in DFT feature and architecture definition for complex SOC Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic Generate DFT related timing constraints and support timing closure with backend engineer DFT test patterns generation, simulation and debug Requirements: Bachelor or master degree, majoring in microelectronics, electronic engineering , computer science or related Good knowledge of digital IC design Good knowledge of DFT knowledge such as Scan/ATPG, MBIST and boundary scan is a plus Good knowledge of Verilog HDL Strong commitment to schedule and work quality, good team player Good English capabilities More information about NXP in Greater China... #LI-d6f4