Senior ASIC Engineer

Overview

• As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing.
• Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios.
• The PMU IP consists of a RISC-V core and custom-designed control logic.
• It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points.
• We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter.
• What you’ll be doing: Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features.
• Learn how PMU's function impacts the system and support the silicon debug.
• Implement the micro-architecture to RTL design.
• What we need to see: BS / MS in electrical / computer engineering.
• 3+ years working experience, with preference given to those with MS or equivalent experience.
• Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in USA and India.
• Familiar with frontend ASIC design.
• Ways to stand out from the crowd: Experience on active power/low power design.
• For example, AVFS, DVFS, PG, RG, CG, etc.
• Play similar role in other system-level control features if not power related.