Staff Engineer, ASIC STA

What You'll Do

• Responsible for Block/ Chip Tile Synthesis to achieve the best PPA.
• Constraint Generation & Timing closure for Block and Full Chip SOC for complex hierarchical Designs for all the Modes.
• Interaction with Design, DFT, IP&PD teams for Timing Convergence & Resolving Constraint Conflicts .
• Able to work on low power Intent & verify low power intent with minimal supervision.
• Responsible for Logical equivalence checks & Low Power Checks.
• Early RTL analysis for Clocking, Power , DFT coverage & suggestions to Designer on the improvements.
• Support Verification team to enable GLS.
• Preferred Skills: ·Strong verbal communication skills ·Cadence PnR tools ·Formal verification experience ·Digital electronics and microprocessors experience About Micron Technology, Inc.
• We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all .
• With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands.
• Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.
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