SR Engineer, ASIC DFT

What You'll Do

• Accountable for innovative DFT implementation(Scan, MBIST, LBIST & Boundary Scan) at the RTL and Gate level for a given SOC at Hard macro and chip top level.
• Generate and validate ATPG patterns using simulations.
• Shall Validate the DFT implementation using RTL and Gate level simulation.
• Work with Multi-functional Teams on STA, Synthesis, LEC, CLP, verification & Validation.
• Support the Silicon bring up activities to guarantee the highest stability of the test patterns/program.
• Chip in to the overall DFT methodology development.
• Nice to have Skills/Experience :- Shall have Knowledge of IEEE 1149.6, 1500 and 1838.
• Good experience on Hierarchical Scan implementations with core wrapping concepts Experience in handling multi-clock domains and low power design implementation.
• Knowledge/Experience on SSN, 2.5D or 3D IC DFT implementation.
• Communicate effusively with multi-functional functional teams in different geographies and time Zones.
• Time management and multi-tasking skills.
• Job Location: You will be joining part of growing team in Hyderabad or Bangalore.
• We value People and our dedication is to reward people with multiple Micron benefits that include PTO and medical benefits to name the few.
• About Micron Technology, Inc.
• We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all .
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