Senior SOC Physical Design Engineer, HBM

About This Role

• Responsibilities will include, but are not limited to: Support physical implementation of SoC blocks from floorplanning through placement, clock tree synthesis (CTS), routing, and optimization to meet performance, power, and area targets.
• Assist with setup and hold timing closure across multi‑mode, multi‑corner (MMMC) scenarios using industry tools such as PrimeTime or Tempus under guidance of senior engineers.
• Collaborate with RTL design and integration teams to ensure correct clocking, reset strategies, and power intent implementation throughout the design.
• Integrate and implement complex intellectual property (IP) blocks including controllers, interfaces, memory built‑in self‑test (MBIST), design for test (DFT) logic, buffers, and PHY‑adjacent logic with focus on timing and physical correctness.
• Run and debug physical signoff checks such as design rule checking (DRC), layout versus schematic (LVS), and timing signoff, addressing violations with support from signoff experts.
• Work with DFT teams to ensure scan and MBIST logic are physically clean and do not negatively impact timing, congestion, or routability.
• Participate in tapeout readiness activities including engineering change order (ECO) flows, checklists, design reviews, and post‑silicon debug by correlating silicon behavior with physical design, static timing analysis, and power analysis.
• Apply hands‑on experience with electronic design automation tools and methodologies while working effectively in a cross‑functional, global team environment.