Opens cadence.wd1.myworkdayjobs.com in a new tab
About This Role
- About the team: Our team deliver many high-performance products based on the industry’s most advanced technology with high frequencies up to 8800MHz.Our product processes include TSMC 2nm/3nm/5nm/7nm/12nm and Samsung 2nm/4nm/5nm/7nm/8nm/10nm, etc.
- In the team you will face great challenges such as FP, CTS, STA, etc.
- At the same time, you will get rich experience and advanced methodology.
- Job Responsibilities: Focus on high-speed digital DDR PHY IP physical implementation, develop necessary scripts or tools to enhance current PD design flow.
- Work in product projects, including but not limited to: complete the project tasks; solve design issue and provide flow to check and avoid similar issue; analyze and summarize PPA optimization methodologies and results, implement optimal design parameters and flows for different projects.
- Job Requirement: -BS with minimum 7+ years of experience.
- MS with minimum 5+ years of experience. -Good physical design experience in the digital implementation domain including Floorplan, CTS, STA, Physical verification, Power analysis. -Solid background in circuits, electronics, physics, be willing to learn new technology for cutting edge process node and advanced design methodology. -Skilled in scripting language, such as Perl, C shell, TCL, Makefile, Python. -Familiar with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime, etc.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
Your application goes straight to Cadence Design Systems.
More from Cadence Design Systems (614 roles)
Cadence Design Systems
Ontologies & Knowledge Graphs (Agentic AI, Surrogates, Physical AI)
PUNE 05|Other
Cadence Design Systems
Ontologies & Knowledge Graphs (Agentic AI, Surrogates, Physical AI)
PUNE 05|Other
Cadence Design Systems
Software Engineer II: R&D Hardware Verification
BELO HORIZONTE|Verification
Opens cadence.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹5-11 LPA to ₹38-65 LPA
Open roles at Cadence Design Systems
614 positions
Job ID
/job/SHANGHAI/Design-Engineer---Physical-Design_R55332
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Physical Design roles
Micron Technology
Physical Design Engineer
Jalisco, Mexico|Physical Design
Micron Technology
Principal Engineer, ASIC Physical Design
Hyderabad - Phoenix Aquila, India|Physical Design
Micron Technology
Staff Engineer, Physical Design
Hyderabad - Phoenix Aquila, India|Physical Design
Marvell Technology
Physical Design Intern
Petah-Tikva|Physical Design