Principal SoC DFT Engineer, HBM

What You'll Do

• will include, but are not limited to: Own SoC-level DFT implementation, including scan, MBIST, LBIST (as applicable), boundary scan (JTAG), and test access architectures for HBM base-die designs.
• Drive DFT architecture definition early in the design cycle, ensuring alignment with SoC integration, floor planning, timing, power, and physical design constraints.
• Implement and integrate DFT logic at the block, subsystem, and full-chip levels, working closely with RTL and integration teams.
• Own DFT flow execution and signoff, including lint, CDC, DFT rule checks, ATPG readiness, and coverage closure.
• Collaborate with physical design teams to ensure DFT solutions are optimized for placement, routing, timing closure, and DRC/LVS signoff.
• Work closely with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, and smooth silicon bring-up.
• Support pre-silicon debug of DFT-related issues and assist with post-silicon bring-up and yield/debug analysis.
• Partner with CAD and methodology teams to define, improve, and standardize DFT flows across HBM SoC programs.
• Required Experience Bachelor’s degree or higher in Electrical Engineering, Computer Engineering, or related field. 7+ years of relevant experience in SoC design, DFT, or implementation for complex digital ASICs or SoCs.
• Job title and level can scale depending on experience and qualifications.
• Successful candidates for this position will have: Experience with scan insertion, MBIST/LBIST architectures, JTAG/boundary scan, and ATPG concepts.
• Familiarity with full RTL-to-GDS SoC flows, including interaction between DFT, synthesis, STA, and physical design.
• Experience working with large, complex SoCs involving multiple IPs and subsystems.
• Proficiency with industry-standard EDA tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Familiarity with scripting languages (Python, Tcl, Perl, etc.) for flow automation.
• The US base salary range that Micron Technology estimates it could pay for this full-time position is: $162,000.00 - $344,000.00 a year Additional compensation may include benefits, bonuses and equity.
• Our salary ranges are determined by role, level, and location.
• The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations.
• Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training.
• The pay scale is subject to change depending on business needs.
• Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
• Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits.
• As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth.
• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.
• Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.
• Additionally, Micron benefits include a robust paid time-off program and paid holidays.
• For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits .
• Micron is proud to be an equal opportunity workplace and is an affirmative action employer.
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