Principal Digital Design Engineer (m/f/d)
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Salary range — RTL Design in India
Fresher (0-2y)
₹5-12 LPA
Mid (3-5y)
₹12-24 LPA
Senior (6-10y)
₹24-45 LPA
Staff (10+y)
₹40-70 LPA
Typical skills for RTL Design
VerilogSystemVerilogVHDLLogic SynthesisCDCLow Power DesignMicroarchitecture
Common EDA tools
Synopsys Design CompilerCadence GenusSynopsys VCSXilinx Vivado
About RTL Design roles
Designs digital logic at register-transfer level using Verilog/SystemVerilog, creating synthesizable hardware descriptions for ASICs and SoCs
Market insight: RTL designers with sub-7nm tapeout experience command premium salaries. SystemVerilog proficiency is table stakes; low-power design (UPF/CPF) and CDC expertise are strong differentiators.
Full description on Micron Technology’s career page.
Sourced directly from Micron Technology’s career page
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Micron Technology
2635 positions
Job ID
/job/Munich-MDC-Germany/Principal-Digital-Design--m-f-d-_JR91511-1
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