Physical Design Manager

What You'll Do

• Serve as the primary technical owner for physical design and timing closure on assigned blocks, partitions, or subsystems Perform hands‑on physical design and timing analysis , including late‑stage debug and convergence Define and actively drive closure strategy , not just review results Act as a key technical escalation point , stepping in directly when progress stalls Lead and mentor a small team of PD engineers as a player‑coach Provide prioritization, technical direction, and day‑to‑day execution guidance Coordinate closely with STA, RTL, CAD, and Program teams to resolve complex issues Support hiring, onboarding, and ramp‑up of new team members while maintaining technical ownership Communicate execution status, risks, and tradeoffs clearly to engineering leadership What We're Looking For Principal Physical Design Manager (Player‑Coach, Hands‑On) About the Role We are looking for a Physical Design Mananger who will operate in a hands‑on, execution‑first player‑coach role.
• This position combines direct technical contribution with first‑line people leadership.
• The ideal candidate is someone who wants to stay deeply involved in physical design and timing closure while guiding a small team through critical execution phases.
• This is not a pure people‑management role .
• Success in this position is measured by delivery, convergence, and technical ownership , not by team size.
• Technical Qualifications Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or e quivalent professional experience in lieu of a formal degree​ Principal‑level physical design expertise with a proven track record delivering timing‑closed ASICs or complex SoCs Demonstrated success in timing analysis and closure across multiple designs Deep understanding of advanced timing concepts including SI, CDC, LVF, POCV , and related methodologies Strong proficiency with PD and STA tools (e.g., Synopsys PrimeTime or equivalent), scripting, and UNIX/Linux environments Strong written and verbal communication skills with the ability to articulate technical tradeoffs Leadership Experience (Execution‑Focused) Experience leading PD engineers in a first‑line, hands‑on capacity Proven ability to operate as a player‑coach , contributing technically while guiding others Experience mentoring engineers and developing PD talent through active engagement Ability to coordinate execution across cross‑functional teams with clear ownership and accountability Nice to Have Experience owning full‑chip or large‑subsystem PD and timing closure Familiarity with timing methodology and flow development Experience working with multi‑site or globally distributed teams Experience balancing FTE and contractor resources Growth Opportunity This role is scoped as an player‑coach today, with the opportunity to grow into broader leadership influence over time, while remaining technically engaged.
• Expected Base Pay Range (USD) 185,900 - 275,170, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
• The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way.
• Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
• Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
• This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
• As such, applicants must be eligible to access export-controlled information as defined under applicable law.
• Marvell may be required to obtain export licensing approval from the U.S.
• Department of Commerce and/or the U.S.
• Department of State.
• Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-TT1