Hardware & Silicon Validation Principal Engineer

What You'll Do

• Lead SI and PI analysis for high‑speed digital interfaces, from early architecture definition through post‑silicon validation and production enablement. • Perform pre‑layout and post‑layout signal integrity analysis, including channel modeling, eye‑diagram analysis, jitter decomposition, timing margin analysis, and compliance assessments. • Design and analyze power distribution networks (PDN) across die, package, and PCB, including AC impedance analysis, transient simulations, decoupling strategies, and noise mitigation. • Support and optimize high‑speed interfaces such as DDR4/DDR5, HBM, PCIe Gen4/Gen5/Gen6, Ethernet (NRZ and PAM4), and other SerDes‑based links. • Develop and enforce SI/PI guidelines, methodologies, and sign‑off criteria to ensure consistent design quality across multiple programs. • Collaborate with package, PCB, and connector teams to evaluate layout trade‑offs, stack‑ups, materials, and routing strategies impacting end‑to‑end channel performance. • Correlate simulation results with lab measurements, supporting board bring‑up, debug, and post‑silicon characterization using oscilloscopes, TDRs, VNAs, and other lab tools. • Identify and drive resolution for cross‑domain issues involving signal integrity, power integrity, timing, EMI/EMC, and thermal interactions. • Provide technical leadership through design reviews, mentoring engineers and influencing architectural decisions with data‑driven recommendations. • Support customer engagements, field issues, or escalations requiring deep SI/PI expertise.
• What We're Looking For • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience OR Master’s degree in Computer Science, Electrical Engineering or related fields with 5-10 years of experience. • Proven record of technical leadership and ownership across multiple product generations, driving SI/PI excellence from early architecture through production. • Deep expertise in high‑speed signal integrity analysis and design, including transmission line theory, channel modeling, and loss/jitter/noise mechanisms. • Extensive hands‑on experience with advanced high‑speed interfaces, such as DDR4 / DDR5 / LPDDR, HBM, PCIe Gen4 / Gen5 / Gen6, Ethernet (25G/50G/100G+ NRZ and PAM4 SerDes), high‑speed chip‑to‑chip links • Strong understanding of package, PCB, and connector effects on end‑to‑end channel performance. • Expertise in pre‑layout and post‑layout SI simulations, timing margin analysis, eye‑diagram analysis, jitter decomposition, and compliance validation. • Deep knowledge of power distribution network (PDN) design, including on‑die, package, and board‑level power delivery. • Expertise in AC and transient PI analysis, impedance target formulation, decoupling strategies, VR design, and noise mitigation. • Practical experience analyzing and resolving simultaneous switching noise (SSN), ground bounce, and rail collapse issues. • Expert‑level proficiency with industry‑standard SI/PI tools, such as Cadence Sigrity (PowerSI, SystemSI, OptimizePI), Siemens HyperLynx, Keysight ADS / EMPro, Ansys HFSS / SIwave, Equivalent extraction and EM simulation tools. • Experience collaborating with memory, SerDes, PHY, silicon, packaging, thermal, mechanical, and validation teams to resolve cross‑domain issues. • Hands‑on experience supporting board bring‑up, lab debug, and post‑silicon validation, correlating simulation results with lab measurements. • Ability to act as a technical authority and decision maker for SI/PI architecture and design trade‑offs across programs. • Strong communication skills, capable of clearly presenting technical risks, trade‑offs, and recommendations to engineering leadership and executive stakeholders.
• Expected Base Pay Range (USD) 150,680 - 225,700, $ per annum The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.
• The expected base pay range for this role may be modified based on market conditions.
• Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments.
• Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.
• Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
• We look forward to sharing more with you during the interview process.
• Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .
• Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
• These tools must not be used to record, assist with, or enhance responses in any way.
• Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time.
• Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
• This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR).
• As such, applicants must be eligible to access export-controlled information as defined under applicable law.
• Marvell may be required to obtain export licensing approval from the U.S.
• Department of Commerce and/or the U.S.
• Department of State.
• Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-SA1