Digital Design Engineer

Overview

• About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world.
• Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
• At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow.
• For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
• Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools.
• You will have the opportunity to use your extensive design and CAD knowledge to participate in defining the whole organization's design infrastructure, methodology and workflows.
• What You Can Expect Develop and maintain leading-edge RTL validation flows, such as RTL linting/CDC or timing constraint validation, addressing the needs of Marvell’s various Business Units.
• Keep up with process and tool evolutions, enable new technologies into design team execution flows.
• Leverage AI tools to enhance the efficiency and accuracy of CAD flows.
• Contribute to the deployment and support of these flows.
• Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform.
• Generate, collect, centralize and disseminate knowledge around RTL methodology.
• Interface with EDA vendors for optimal tool usage.
• What We're Looking For Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.
• Good level in scripting in Tcl and Python in the context of flow development.
• Proficiency in Verilog / SystemVerilog Design and Verification.
• Experience in RTL linting tools, including clock domain crossing (CDC).
• Experience in git revision control.
• Knowledge in Equivalence Checking for both RTL to gates and gates to gates in LEC or in Formality is highly desirable Demonstrate good analysis and problem-solving skills.
• Out-of-the-box thinking.
• Team player with good verbal and written communication skills.
• A keen eagerness to learn new skills is also important.