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About This Role
- This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.
- We're looking for a hands-on SoC Design Verification Engineer to drive verification for complex SoC/IP blocks.
- You will own verification planning, UVM testbench development, test content creation (directed and constrained-random), coverage closure, and debug across block, subsystem, and SoC levels.
- You'll collaborate closely with design, architecture, firmware, and validation teams to deliver high-quality silicon on schedule.
- Key Responsibilities Own the verification lifecycle for one or more IPs/subsystems/SoC top-level features: requirements decomposition, test plan definition, coverage strategy, execution, and signoff.
- Architect and implement UVM environments (agents, drivers, monitors, sequencers, scoreboards, reference models), with scalable, reusable components.
- Develop test content: constrained-random sequences, scenario tests, stimulus libraries, checkers, and assertions.
- Debug failures quickly and methodically across simulation and emulation (waveforms, logs, assertions, checkers, reference model mismatches).
- Drive coverage closure (functional and code coverage): define, measure, analyze holes, and implement closure strategies.
- Leverage assertions (SVA) and formal where appropriate to strengthen verification quality and accelerate bug find.
- Integrate VIPs (e.g., AXI/ACE/PCIe/DDR) and coordinate with external/internal IP teams for models, checkers, and coverage.
- Collaborate cross-functionally with RTL design, architecture, DV, DFT, performance, firmware, and post-silicon validation to ensure feature completeness and testability.
- Continuously improve flows: contribute to methodology, regressions, CI/CD, and verification infrastructure (e.g., Makefiles, Python utilities, farm scripts).
- Document plans, environments, and results; present status, risks, and signoff evidence to stakeholders.
- Behavioral Traits Problem ‑ Solving Mindset: Approaches complex technical challenges with curiosity, creativity, and structured analytical thinking.
- Collaboration Skills: Works effectively with cross ‑ functional engineering teams, seeks input from partners, and communicates clearly in both technical and non ‑ technical contexts.
- Adaptability and Learning Agility: Quickly learns new tools, technologies, and methodologies; comfortable working in evolving development environments.
- Attention to Detail: Delivers high ‑ quality, reliable, and scalable software solutions with a focus on robustness, validation, and secure coding practices.
- Results ‑ Oriented: Prioritizes effectively, manages time well, and drives solutions to completion in a fast ‑ paced engineering environment.
- Innovation and Continuous Improvement: Looks for opportunities to optimize tools, simplify workflows, and introduce new methodologies that enhance engineering efficiency.
Requirements
- are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering or in a related field 5+ years of experience in: SoC/IP design verification experience UVM/SystemVerilog development expertise (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms).
- Test planning experience: translating architectural/RTL specs into measurable, coverage-driven verification plans.
- Proven debug skills in simulation/emulation (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision).
- Coverage-driven verification: functional coverage modeling, code coverage analysis, coverage closure workflows.
- Scripting proficiency (e.g.
- Python, Shell, Make/CMake) for automation, regressions, and data analysis.
- Advance English level.
- Must have unrestricted, permanent right to work in Mexico (this role is not eligible for vi-sa or immigration sponsorship).
Nice to Have
- SoC-level verification experience: fabric/interconnect, security, Experience with standard protocols: AXI/ACE/CHI, PCIe, LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet; integrating and customizing VIP.
- Assertion-based verification (SVA) and formal (JasperGold/VC Formal/PropCheck) for property checking and bug hunting.
- Power-aware verification (UPF/CPF), isolation/retention, multi-voltage domains.
- Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction-level acceleration, hybrid verification.
- Performance/latency/throughput test content and checkers; scoreboard/reference model design for complex data paths.
- Exposure to C/C++/SystemC reference models or firmware-aware verification.
- Experience leading small teams, mentoring, or driving signoff for a tapeout.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
712 positions
Job ID
/job/Mexico-Guadalajara/SoC-IP-Design-Verification-Engineer_JR0282555
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