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About This Role
- The Role and Impact Support development and maintenance of assembly design rules that addresses the capabilities and constraints of advanced silicon packaging and heterogeneous integration.
- Contribute to package assembly design kit by creating and evaluating test cases for different assembly configurations.
- Evaluate constraints arising from multidie integration, including flipchip, substrate routing, bump placements, and interconnect patterns, ensuring compliance with documented assembly rules.
- Interpret design rule impacts on manufacturability, yield, and system-level integration requirements.
- Assist in reviewing bump layouts and propose corrections across a design life cycle.
- Prepare reports summarizing rule checks, violations, and recommendations, helping maintain an up to date, well organized assembly rule knowledge base.
- Key Responsibilities Assist in the validation, debugging, and testing of silicon products, from initial bring-up to high-volume manufacturing.
- Collaborate with cross-functional teams to resolve engineering challenges, optimize product performance, and improve yield and reliability.
- Learn and apply principles of design for test (DFT), manufacturing (DFM), and debugging techniques to support product lifecycle and qualification.
- Conduct root cause analysis and problem-solving to identify and address engineering issues effectively.
- Contribute to the development and optimization of test engineering processes, tools, and documentation.
- Support the analysis and optimization of power and performance metrics for silicon products.
- Continuously build technical knowledge and skills through hands-on experience and collaborative projects.
Requirements
- Currently pursuing a Masters or PhD in Electrical Engineering, Computer Engineering, or a related field with a focus on semiconductor devices or silicon testing. 3+ months experience with packaging assembly design.
- Experience with root cause analysis and problem solving in a technical environment.
- Familiarity with technical documentation and communication of engineering results.
- Preferred Qualifications Demonstrated ability to collaborate effectively with cross-functional teams in a research or engineering environment.
- Knowledge of design for debug (DFD) principles and their applications in silicon validation.
- Strong interest in continuous learning and improvement within the semiconductor domain.
- Passion for making meaningful contributions to innovative technologies and products.
- If you are looking to apply your academic expertise to real-world challenges and accelerate your career in silicon product engineering, we encourage you to take the next step with Intel.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $89,200.00-120,700.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Our standard internship rates are based on your degree, location, and the job role.
- Your recruiter can share more about the specific compensation range for your preferred location and job role during the hiring process.
Sourced directly from Intel’s career page
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Specialisation
Open roles at Intel
713 positions
Job ID
/job/US-Oregon-Hillsboro/Silicon-Product-Engineering-Graduate-Intern_JR0284243
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