Silicon Packaging Design Engineer

About This Role

• The Role and Impact: Intel is seeking a motivated and innovative Layout Design Engineer to join our team of world-class semiconductor professionals.
• In this role, you will be at the forefront of designing the physical layout of of Intel's silicon that are used for its packaging technology.
• You will collaborate with customers, electrical engineers (for signal integrity and power delivery) to optimize performance, reliability, and manufacturability, driving innovation and efficiency across our cutting-edge products.
• As a Layout Design Engineer, you will play a critical role in ensuring Intel's continued leadership in the semiconductor industry, contributing to advanced methodologies and groundbreaking solutions.
• Key Responsibilities: Develop custom layouts for Intel's silicon used for its packaging technology.
• Perform detailed physical array planning, area optimization, and signal and power routings.
• Design and verify standard cell libraries, ensuring compliance with design rules, PDK specifications, and reliability requirements.
• Execute layout verification processes, including checks for electron migration, voltage drop (IR), self-heat, ESD, and other reliability metrics.
• Use custom auto-routers and placers to efficiently construct layouts and optimize designs.
• Troubleshoot design, tool, and methodology issues related to layout construction.
• Provide feedback to circuit design engineers on feasibility studies and implement circuit enhancement requests.
• Develop and drive innovative layout methodologies to improve productivity, quality, and manufacturability.
• Utilize EDA tools and design flows for floor planning, routing, reliability verification, and performance optimization.
• Collaborate with cross-functional teams to ensure seamless execution of silicon tape-in.