Senior USB IP Design Verification Engineer

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The Role and Impact As an IP Design Verification Engineer, you will play a critical role in ensuring the functionality, quality, and efficiency of Intel's cutting-edge USB IP designs.
Working within a fast-paced and innovative environment, you will be responsible for verifying IP logic to meet architectural specifications and standards, shaping the future of Intel's technology portfolio.
Your efforts will directly impact the reliability and performance of products used globally, contributing to Intel's mission to create world-changing technology that improves the lives of every person on the planet.
Key Responsibilities : Develop functional verification plans and test benches to ensure comprehensive coverage of microarchitecture specifications.
Execute verification strategies through system simulation models to analyze power, timing, and functionality while identifying and resolving bugs.
Implement corrective measures to address failing tests and debug issues in the presilicon environment.
Collaborate with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features.
Maintain and improve functional verification infrastructure and methodologies to support ongoing innovation.
Document test plans and lead technical reviews with design and architecture teams to ensure alignment with project goals.
Drive improvements in test coverage, efficiency, and execution time through innovative problem-solving and validation techniques.

Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or equivalent.
At least 6-8 years of industry experience in RTL design verification with expertise in SystemVerilog and UVM/OVM methodologies.
Proficiency in designing test plans, developing testbench infrastructure (including monitors, scoreboards, BFMs), and creating coverage points and assertion checks.
Familiarity with pre-silicon verification tools such as VCS/Synopsys and scripting languages like Python, Perl, or Shell for automation.
Understanding of high-speed IO IPs such as USB, PCI Express, or AMBA protocols.
Comprehensive knowledge of VLSI design flows, structural and physical design methodologies, and power-aware simulation techniques.

Advanced degree in a relevant field (Master's or PhD).
Experience with SoC-level validation environments and subsystem interoperability validation.
Expertise in power-aware design, simulation, and validation flows for low-power architecture.
Strong analytical and debugging skills with a demonstrated ability to solve complex technical challenges.
Prior experience in collaborating within diverse, cross-functional teams to achieve project milestones.
Effective communication, initiative, and adaptability to dynamic, fast-evolving environments.
Join Intel and drive innovation that shapes the future of technology.
Apply now to become part of a team where your expertise will make a meaningful impact.

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