Senior STA Engineer

About This Role

• The HIPD SAM team is responsible for delivering end-to-end Static Timing Analysis (STA) and timing sign-off for Intel's Client, Server and ASIC Hard-IP portfolios, as well as advanced test Chips for IP and SoC functional blocks and Subsystems.
• Role Summary The Senior STA Engineer (Staff - Grade 8) independently owns hands-on, end-to-end Static Timing Analysis and timing closure of complex multi-GHz blocks and full-chip designs at 3nm and below.
• Key Responsibilities • Independently own block-level and full-chip STA from netlist handoff through final timing sign-off for multi-GHz designs. • Drive timing closure across multiple modes, corners, and scenarios (MCMM). • Define and own PVT corner definitions and extraction corner alignment. • Lead and execute STA methodologies including POCVM/AOCV/LVF. • Define and apply timing margining and guard-band strategies for silicon robustness. • Analyze and debug complex setup/hold, clocking, and constraint-related timing issues. • Develop scripting and automation in TCL/Python to improve analysis efficiency and quality. • Partner with Physical Design, Logic, Clocking, and Methodology teams. • Mentor junior engineers while remaining hands-on.