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About This Role
- Intel is transforming from an Integrated Device Manufacturer (IDM) to a leading foundry service provider, offering world-class manufacturing capabilities to customers worldwide.
- Our Manufacturing Development and Customer Engineering (MDCE) organization is at the forefront of this transformation, focusing on yield improvement, performance optimization, and exceptional customer service delivery.
- We are seeking a Principal Collateral Device Engineer to join our team within MDCE.
- This role requires regular onsite presence to fulfill essential job responsibilities and will creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
- Key Responsibilities: Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects.
- Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
- Experience in scribe line layout design and process monitoring structure development.
- Proficiency in design rule development, validation, and waiver management processes.
- Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
- Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
- Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
- Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
- Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
- Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
- Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.
Requirements
- to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements
- Master’s degree in Electrical Engineering, Physics, or related field 15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development Preferred Qualifications: Ph.D. degree in Electrical Engineering, Physics, or related field 15+ years of experience in CMOS device engineering and collateral development Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs Experience with design rule checker (DRC) development and physical verification flows Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization Knowledge of mask generation including Boolean/OPC .
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $224,970.00-317,600.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
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Specialisation
Open roles at Intel
664 positions
Job ID
/job/US-California-Santa-Clara/Principal-Collateral-Device-Engineer_JR0285235
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