Pre-si Verification Engineer

What You'll Do

• Define and develop SoC / subsystem / IP verification plans aligned to architecture specifications • Build and maintain SystemVerilog/UVM-based testbenches and verification environments • Develop constrained-random and directed test scenarios and validation content • Execute simulation and emulation-based verification to validate functionality, power, and performance • Perform debug and root-cause analysis of RTL and testbench failures in pre silicon environment • Analyze and drive functional, code, and assertion coverage closure • Collaborate with architecture, RTL design, post silicon, and validation teams • Document verification plans and participate in design/verification reviews • Continuously improve verification methodology, infrastructure, and automation flows • Incorporate learning from post silicon validation to enhance future verification coverage • Good at leveraging AI across verification coding, debugging , quality sign-off requirements. • Minimum 8-15 year of relevant experience in SoC/subsystem/IP level verification • Qualifications BE or B Tech or M Tech ECE or Computer Science with 8-15 years front-end pre-si verification. • Lead verification activities while mentoring and guiding junior team members to ensure high-quality project execution.