Mixed Signal Logic Design Engineer

About This Role

• The Memory PHY Group (MPG) within the Central Engineering Group (CEG) is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations for the cutting-edge DDRPHY IPs.
• You will be responsible for overseeing definition, design, verification and your responsibilities will include but are not limited to - defining architecture and microarchitecture features of the block being designed, implementing RTL in SystemVerilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools for Lint, CDC, RDC, Voltage domain crossings, Synthesis QA checks etc, creating FE packages for IP milestones that meet SoC Collateral requirements, create innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc.
• You will also have an opportunity to contribute to automating various Front End Tool, Flows and Methodologies and innovating the IP RTL delivery to Validation teams, Backend Teams as well as SoC teams.
• The ideal candidate should exhibit excellent written and verbal communication skills which are critical in a small, fast-moving team.
• As part of a growing, dynamic business, the candidate must be successful working with many cross functional teams and manage multiple tasks and changing requirements, in an innovative environment.
• Objectives of the position - Own and deliver the logic design of Mixed Signal IPs. - Continuously drive improvement in the Turnaround time, robustness of Logic design via Architecture engagement and Tools/Methodology improvements. - Drive area/power of IPs and come up with improvements on IP Area/Power metrics. - Critical Decision making on Technical issues.