Opens intel.wd1.myworkdayjobs.com in a new tab
About This Role
- Join Intel as a Mixed Signal Design Verification Engineer and play a crucial role in shaping the future of cutting-edge technology.
- In this role, you will be at the forefront of ensuring Intel's mixed signal logic components meet the highest standards of functionality, performance, and reliability.
- As part of a world-class team, your work will directly contribute to the design of advanced architectures and technologies that will power tomorrow's innovations.
- Responsibilities will include but are not limited to: Develop and execute comprehensive verification plans for mixed signal logic components to ensure alignment with microarchitecture specifications.
- Design and implement test benches and verification environments using advanced methodologies such as OVM and UVM.
- Perform system-level simulation to verify functionality, analyze power and timing, and identify potential design issues.
- Collaborate with digital and analog architects, RTL developers, and physical design teams to optimize verification strategies and meet performance, power, and functional goals.
- Debug presilicon issues by replicating, root causing, and implementing corrective measures for failing tests.
- Create and maintain analog behavioral models and contribute to the development of reusable verification infrastructure and methodologies.
- Document test plans, verification results, and drive technical reviews with design and architecture teams.
- The ideal candidate should show the following behavioral traits: Exceptional problem-solving skills, willing to debug complex presilicon issues.
- Strong collaboration and communication skills, with a track record of working effectively with cross-functional teams.
- Passion for innovation and a commitment to excellence in engineering.
Requirements
- are required to be initially considered for this position.
- A Bachelor's or BS degree and/or equivalent knowledge in a specialized field, with at least 3 years of relevant experience, OR A Master's degree and/or equivalent knowledge in a specialized field, with at least 2 years of relevant experience, OR PhD and/or equivalent knowledge in a specialized field, with at least 1 year of relevant experience, Experience listed above should be a combination of the following: Verification methodologies such as OVM and UVM.
- SystemVerilog and Verilog for test environment and design verification.
- Developing test environments for functional verification of mixed signal logic components.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
- Experience with power intent design and/or UPF (Unified Power Format) modeling.
- Intel offers a dynamic and inclusive environment where your expertise will be valued, your contributions will make a difference, and your career will thrive.
- Join us in driving technical excellence and building the future of computing technologies.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
Opens intel.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
664 positions
Job ID
/job/US-California-Folsom/Mixed-Signal-IP-Verification-Engineer_JR0284918-1
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Verification roles
Micron Technology
Staff engineer , ASIC AMS Verification
2 Locations|Verification
Analog Devices
Director, Design verification engineering
India, Bangalore, RMZ|Verification
Cadence Design Systems
Software Engineer II: Verification IP Development
BELO HORIZONTE|Verification
Cadence Design Systems
Senior Emulation Design Verification AE
HOME CA|Verification