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About This Role
- The Role and Impact As a Mixed Signal Design Verification Engineer, you will play a pivotal role in verifying and enhancing the functionality of mixed signal logic components, ensuring Intel's products meet the highest standards of quality, performance, and innovation.
- In this role, you will collaborate with cross-functional teams to validate cutting-edge IPs, pushing the boundaries of technology and innovation.
- Your work will directly contribute to Intel's leadership in delivering best-in-class solutions that power the future of computing.
- Key Responsibilities - Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications. - Develop comprehensive IP verification plans, test benches, and verification environments to achieve thorough coverage of mixed signal microarchitecture specifications. - Define and execute verification plans, including running system simulation models, analyzing power and timing, and identifying and resolving design bugs. - Debug failing tests in the presilicon environment through root cause analysis and implement corrective measures to ensure design functionality. - Collaborate closely with digital and analog architects, RTL developers, and physical design teams to improve architectural and microarchitectural features. - Lead technical reviews of test plans and validation proofs with design and architecture teams while documenting findings and ensuring thorough validation coverage. - Maintain, refine, and enhance functional verification methodologies, infrastructure, and tools to keep pace with industry advancements.
Requirements
- Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field. - 4-12 years of experience with a Bachelor's degree, or 3-10 years of experience with a Master's degree in ASIC or SoC verification. - Excellent knowledge on DDR4/DDR5/LP5/LP6 protocol - Expertise in SystemVerilog, UVM, and Verilog for mixed signal verification. - Hands-on experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa. - Strong scripting skills in Python, Perl, or Tcl for testbench automation and process efficiency. - In-depth knowledge of standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi-clock domain mixed signal designs. - Proficiency in constraint-random test generation, root cause analysis, and debugging of complex mixed signal designs.
- Preferred Qualifications - Experience with low-power design techniques, including UPF and clock gating, to optimize power consumption. - Familiarity with Formal Property Verification tools and version control systems such as Git or Perforce. - Strong collaboration and communication skills, with the ability to thrive in a dynamic, multidisciplinary team environment.
- Join us to drive verification excellence and shape the future of technology at Intel.
- Apply today to become part of our mission to deliver transformative innovations.
Tools & Skills
EDA Tools
Languages
Sourced directly from Intel’s career page
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
646 positions
Job ID
/job/India-Bangalore/Mixed-Signal-Design-Verification-Engineer_JR0285526-1
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