Memory Layout Lead

About This Role

• You will be a key member of the Corporate Memory Organization (CMO) Layout Team, driving advanced layout design development for Memory Compilers.
• In this senior role, you will work with broadly defined parameters on complex and non-standard assignments while providing technical leadership and mentorship.
• Your responsibilities will include but not be limited to: Core Technical Responsibilities: Drive physical layout implementation of memory building blocks including control circuits, sense amplifiers, I/O blocks, bit cell arrays, and decoders within a compiler framework, demonstrating deep understanding of memory compiler floorplans and top-level integration strategies.
• Bridge cross-functional collaboration between circuit engineering, design automation, and mask design teams, serving as the technical interface and subject matter expert.
• Execute comprehensive layout development encompassing transistor/device cell level planning, layout implementation, assembly, and advanced routing techniques for next-generation memory technologies.
• Demonstrate mastery of all layout aspects including advanced Computer-Aided Design (CAD) tool utilization, productivity macro development, and deep expertise in layout methodologies and workflow optimization Technical Leadership and Decision Making: Provide expert engineering judgment for critical decision-making and complex design trade-offs, including advanced IR drop analysis and mitigation, Reliability Verification (RV) analysis, ECO impact assessment, and project schedule optimization.
• Drive methodology innovation and process refinement for memory compilers in close collaboration with Design Automation (DA) teams and senior/principal design engineers.
• Lead technical assessments of complex layout assignments, establish realistic project timelines, manage multiple concurrent deliverables, and ensure on-time delivery while maintaining quality standards.
• Leadership and Collaboration: Mentor and guide junior layout engineers, providing technical guidance and knowledge transfer.
• Lead cross-functional initiatives and serve as the primary technical contact for memory layout projects.
• Drive continuous improvement in layout efficiency, quality metrics, and design methodologies.
• Collaborate with global teams and effectively communicate complex technical concepts to diverse stakeholders.
• Contribute to strategic planning for future memory compiler architectures and layout automation roadmaps.
• This position offers the opportunity to work on cutting-edge memory technologies while leading technical initiatives and developing the next generation of layout engineering talent. #DesignEnablement Qualifications: Minimum qualifications are required to be initially considered for this position.
• Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.