Memory Debug Engineer

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About This Role

  • Do Something Wonderful! Intel put Silicon in Silicon Valley.
  • No one else is obsessed with engineering and has a brighter future.
  • Every day, we create world changing technology that enriches the lives of every person on earth.
  • So, if you have a big idea, let's do something wonderful together.
  • Join us, because at Intel, we are building a better tomorrow.
  • Who We Are Client Customer Engineering Organization delivers hands-on engineering partnership to PC OEMs, helping them design, validate, and launch next‑generation client platforms.
  • We work closely with partners to integrate next‑gen Intel IA silicon and software, enabling innovative technologies and AI‑powered PC experiences.
  • Who You Are As a Memory Debug Engineer within the Client Customer Engineering team, you will drive the enablement, validation, and complex debugging of memory subsystems for next-generation Intel IA-based Mobile and Desktop platforms.
  • You will provide strategic oversight of memory IO interfaces, ensuring they meet rigorous electrical performance and stability standards at POR target frequencies.
  • Key Responsibilities Strategic Leadership: Define and execute the overarching validation and debug strategy for memory IO interfaces to achieve optimized functional and electrical performance to hit critical production milestones.
  • Complex Issue Resolution: Lead the reproduction and root-cause analysis of high-priority customer-submitted failure sightings.
  • You will oversee component-level debugging within memory subsystems and drive data-driven solutions through deep log analysis.
  • Signal Integrity and Compliance: Ensure all customer memory IO interfaces meet industry-standard electrical signal integrity (SI) compliance and maintain robust system-level margins for stable operation at maximum POR frequencies.
  • MRC Optimization: Define Memory Reference Code (MRC) requirements for validation and margin optimization.
  • You will analyze and optimize MRC steps and values to maximize product quality and reliability.
  • Cross-Functional Influence: Act as the primary liaison between Intel Silicon Engineering, BIOS/Firmware teams, and the customer to resolve architectural bottlenecks.
  • Leadership: Proven ability to manage and drive task force environments to resolve critical bugs.
  • Communication: Exceptional skill in distilling complex electrical eye‑diagram issues into executive‑ready insights and recommendations, and in communicating effectively with cross‑functional teams and external customers.

Requirements

  • The candidate must have a BS/MS/PhD in Electrical Engineering or Computer Engineering with 4+ years of industry experience. 3+ years of experience of DDR4/DDR5, LPDDR4/5 protocols and physical layer functionality/working. 3+ years of experience of debug tools: high-speed oscilloscopes, logic analyzers, margining tools, profilers (e.g.
  • Intel Vtune etc) and protocol exercisers Preferred Qualifications Ecosystem Mastery: knowledge with Intel-specific debug tools (ITP, Scan, or VISA) and mastery of the Intel System Debugger.
  • Standards Influence: Experience participating in JEDEC committees or deep familiarity with emerging standards like CXL (Compute Express Link).
  • Automation: Proficiency in Python for developing automated debug scripts and data visualization tools to speed up root-cause analysis.

Benefits

  • We offer a total compensation package that ranks among the best in the industry.
  • It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
  • Find out more about the benefits of working at Intel .
  • Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
  • Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
  • Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

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