IP Enabling Engineer

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The Hard IP Development Group (HIPD) within Central Engineering Organization of Intel is responsible for developing leadership IPs that power-winning products for Server, Client, Networking SOCs as well as Intel Foundry Customers.
HIPD group develops a broad portfolio of IPs like PLLs, Serial and Parallel IO PHYs like DDR/LPDDR, PCIe, USB, TypeC, UCIe Die 2 Die and Ethernet PHYs.
The IO Post Silicon validation debug group within HIPD team is a dynamic and versatile team of engineers who directly engage with both the IP design teams and SOC customers in IP validation and debug for test chips and products.
These engineers will embody our SOC customer obsession by quickly resolving IP related hurdles by providing hands on debug.
This position is exciting and challenging to exercise your mixed signal design, architecture and post silicon debug expertise across IP and SOC teams.
Your responsibilities will include but are not limited to: Work closely with SOC customers and IP design teams to provide pre silicon to post silicon IP design characterizations, generating test plans and test contents using AI driven tools and pythonSV scripting, SOC board design reviews and recommendations, Signal and Power Integrity simulations and post silicon debugs etc.
Represent the IP team during SOC Power Ons for test chips and products and provide hands on IP enabling support Identify IP related silicon issues, investigate, debug and disposition customer bugs/sightings in a timely manner.

Must have a BS or MS or PhD in Computer Engineering or Electrical Engineering or a Related Field.
Minimum 3 + years of experience in Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die).
Well versed with the lab hardware and software is must.
Must be proficient in using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs.
Familiarity with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc.
Either PHY or Controller experience is good.
Desired Qualifications: Good understanding of signal integrity and power delivery are desired Pre silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validation will be a plus.

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