IP Design Verification Engineer

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About This Role

  • Perform functional verification of IP logic to ensure design will meet specification requirements.
  • Develop IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
  • Execute verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
  • Replicate, root causes, and debugs issues in the presilicon environment.
  • Find and implement corrective measures to resolve failing tests.
  • Collaboration with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
  • Document test plans and drives technical reviews of plans and proofs with design and architecture teams.
  • Maintain and improve existing functional verification infrastructure and methodology.
  • Participate in the definition of verification infrastructure and related TFMs needed for functional design verification.

Qualifications

  • B.Sc. or M.Sc. in Electrical\Computer Engineering. 6+ years of experience in Pre-Si verification Experience in verification at different levels – block, cluster and FC.
  • Strong skills with Specman “e” / SystemVerilog language.
  • PCIe Protocol knowledge - advantage.
  • Solid understanding of verification methodologies, simulation models, and debugging techniques.
  • Experience working with architecture, RTL, and physical design teams.
  • Ability to drive quality improvements, document verification processes, and contribute to technical reviews.

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Intel

Israel, Petah-Tikva

Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
Open roles at Intel
712 positions
Job ID
/job/Israel-Petah-Tikva/IP-Design-Verification-Engineer_JR0281844

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