IP Design Verification Engineer

About This Role

• Your work will involve collaborating with architects, RTL developers, and physical design teams to validate complex architectural and microarchitectural features.
• Through your expertise, you will ensure the robustness of Intel's IP designs, delivering critical contributions to the broader goals of Intel's success.
• Key Responsibilities - Own RTL validation for functional and/or DFx (design for test/debug). - Define verification strategies, methodologies, and detailed test plans for effective RTL validation. - Create Bus Functional Models (BFM) to interface with the IP, monitor transactions, and verify protocol compliance. - Implement and execute test cases, assertions, and functional coverage using SystemVerilog, ensuring alignment with verification plans. - Set up and perform gate-level simulations (GLS) to verify asynchronous and multi-cycle paths. - Debug test failures in RTL and GLS environments, identifying root causes and implementing corrective measures. - Analyze functional and code coverage metrics to identify gaps and achieve full verification coverage. - Automate pre-silicon validation flows by creating tools or scripts, leveraging programming languages such as Tcl, Tk, Perl, or Python. - Collaborate with system and SoC teams on IP integration, ensuring smooth integration and resolving all related issues. - Maintain and enhance verification methodologies, contributing to the improvement of validation infrastructure.