High-Speed SerDes Simulation & Optimization Intern — I/O Next Generation R&D

About This Role

• This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position.
• The IOTS Pathfinding team is seeking a motivated and detail-oriented Engineer Intern to join our team in Guadalajara.
• In this role, you will support readiness and scalability for next-generation high-speed I/O technologies (PCI Express, UPI, CXL, USB) by assisting in technology pathfinding projects critical to future server platforms and Intel's data center leadership.
• You will also develop automated simulation workflows to evaluate full PCIe channel and circuit topologies using simulation tools, extracting realistic channel models, running equalization sweeps, and analyzing results to identify performance bottlenecks and optimization opportunities for next-generation PCIe links.
• You will collaborate with engineers across Intel's I/O community and, as needed, interact with external industry organizations.
• Under mentorship, you will help execute parametric studies and optimization sweeps to explore SI/PI performance and manufacturability tradeoffs, assist with correlating simulations to lab/bench measurements, and contribute to documentation such as a best-practices / design-guidelines report and reusable modeling workflows for design teams.
• Key Responsibilities Develop and maintain an automated end-to-end workflow to simulate PCIe channel/circuit topologies using simulation tools, including repeatable run scripts and standardized inputs/outputs.
• Extract realistic channel models (e.g., S-parameters / behavioral representations as applicable) from full topology descriptions and ensure model quality/consistency for simulation use.
• Set up and run transmitter/receiver equalization sweeps (TX FIR/FFE, CTLE/DFE, adaptation presets, etc. as supported) and capture sensitivity to channel conditions and topology variations.
• Analyze simulation outputs to identify channel performance bottlenecks (e.g., loss, reflections, crosstalk, discontinuities) and propose mitigation actions and topology/parameter improvements.
• Automate post-processing, data reduction, and reporting (plots, tables, margin/compliance metrics) to enable fast comparison across topologies and equalization settings.
• Deliver a reusable simulation testbench (configs, scripts, templates) and a technical report quantifying improvements and documenting recommended settings, assumptions, limitations, and best practices for next-gen PCIe compliance work.
• Present progress and findings in team meetings; collaborate with SI/PI, board/package design, and validation engineers to review results, align on assumptions, and iterate on topology and equalization recommendations.
• Behavioral Traits Eagerness to learn and apply new technical concepts.
• Sense of ownership and accountability for assigned tasks.
• Work effectively in a team-oriented environment.
• Proactive, organized, and able to manage multiple tasks.
• Open to feedback and continuous improvement.
• What You Will Learn Hands-on experience building and running PCIe channel simulations for full circuit/topology use cases (package + board + connectors/cables as applicable).
• Practical exposure to channel model extraction and handling (e.g., S-parameters and related representations) and how model quality impacts link performance predictions.
• Skills in workflow automation for batch runs, parametric sweeps, and post-processing (e.g., scripting, data reduction, plotting) Understanding of transmitter/receiver equalization concepts and sweeps (e.g., TX FIR/FFE, CTLE/DFE) and how EQ settings interact with loss/reflections/crosstalk to determine margin.
• Experience documenting results in a reusable simulation testbench and a summary report (assumptions, limitations, comparisons, and recommendations) oriented towards next-gen PCIe compliance readiness.