Graduate Talent (Server Infrastructure and Test Engineer)

About This Role

• The Role and Impact Intel is seeking a highly driven and technically strong Platform / Infrastructure Test Development Engineer to support server infrastructure and execute high-complexity engineering tasks across global environments.
• In this role, you will be the backbone of critical validation and infrastructure operations, ensuring platform stability, test readiness, and uninterrupted availability for advanced simulation and validation workloads.
• Your work will directly impact global engineering productivity, thirdparty simulation tools, and Intel's ability to deliver robust, high-quality platforms at scale.
• This is a unique opportunity to operate at the intersection of server infrastructure, test development, validation, and domain-level debugging, collaborating with global teams while owning mission-critical systems.
• Key Responsibilities Server Infrastructure Support Support server and GPU infrastructure, ensuring high availability, reliability, and performance across validation and simulation environments.
• Plan and execute critical server and GPU upgrades, minimizing downtime and preventing disruption to third-party simulation tools.
• Proactively identify infrastructure risks and performance bottlenecks, driving preventive actions to sustain continuous operations.
• Technical Support and High-Complexity Engineering Provide deep technical support, debugging, validation, and script maintenance across global sites, acting as a key escalation point for complex platform issues.
• Debug platform-level failures spanning software, firmware, test content, and infrastructure, ensuring rapid root-cause identification and resolution.
• Support platform bring-up and cross-site issue replication to accelerate debug closure.
• Domain Expertise and Test Enablement Apply strong software domain knowledge using Python, and C/C++ to develop, maintain, and enhance validation scripts and automation frameworks.
• Perform board level DFT-related analysis, including datasheet interpretation, pin identification, and signal-level understanding to support In Circuit Test development.