Graduate Talent (ISCP SV Design Verification Engineer)

About This Role

• Develops pre-silicon functional validation strategy, test plan, test suite, test methodologies for state-of-the-art SoC/chipset. -Collaborates with architects, micro-architects, design and system validation teams for SoC validation strategy, technical readiness and failure disposition. -Performs low level and complex debug for multiple systems, subsystems within a product, or at the SoC level for Intel products. -Applies deep understanding of SoC design, architecture, firmware, and software to resolve triage failures, marginality issues, and conduct root cause analysis. -Defines, develops, and implements techniques for faster debug at the SoC and platform level and isolates failing components of a system.