E-Core CPU Design Automation Engineer

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About This Role

  • E-core (formerly known as ATOM), Intel's most efficient CPU Technology team is looking for a highly motivated and technically savvy experienced individual to join our team as Design Automation Engineer.
  • In this position, you will participate in the support and development of CAD solutions for the design of Intel products.
  • Your responsibilities will include but will not be limited to: Defining, implementing and drive project execution by supporting the methodologies and EDA tools necessary to verify backend signoff flows using standard-cell based designs.
  • Work closely with Circuit/Physical Designers to drive solutions in 1 or more of areas, including Circuit Simulation, Static Timing Analysis (STA), Formal-Equivalence Checking, Electrical Rule Checks (ERC), Static Noise analysis, Active/Dynamic/Leakage Power Analysis, LVS, Power-Rail Integrity, Extraction or ECO.
  • Develops and tests Engineering Design Automation tools, creates flows/scripts to analyze and test design methodologies including driving new innovations to EDA tool vendors.
  • Develop custom optimized solutions to address design requirements for leading-edge process technologies.
  • Validate and drive continuous innovation of PDK technology, library files and other collaterals used for standard cell design, layout, and signoff with EDA CAD tools.
  • Proficiency in benchmarking QOR and provide design guidance for better power optimization and/or techniques for frequency improvement and/or tool runtime improvement.
  • Create flows/scripts to analyze, test and improve design methodologies, including through Machine Learning, and look for inefficiencies.
  • Contribute to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Document and help with guidelines/specs.
  • The ideal candidate should exhibit the following behavioral traits: Good inter-personal, clear communication and good teamwork skills.
  • A can-do attitude driven by research and thriving on challenges.
  • Self-motivator with strong problem - solving skills.
  • Willing to handle multiple projects simultaneously and prioritize to project timelines.
  • Good communicator who can accurately perform a deep dive to assess and summarize issues to management.
  • Takes ownership to provide recommendations and drives solutions through to completion.

Qualifications

  • Candidate must have a Bachelor's degree in Electrical/Computer Engineering with 3+ years of experience - OR - a Master's degree in Electrical/Computer Engineering with 2+ years of experience.
  • Deep understanding of most, if not all Circuit Simulation , Physical Design and Verification Tools, Flows and Methods used in VLSI back-end custom-transistor based designs.
  • Expertise using industry standard Engineering Design Automation (EDA) VLSI tools from 1 or more of Cadence , Synopsys, Mentor Graphics in one of more of the following areas of: Circuit Simulation , STA, Power, ECO, LVS, Power-rail integrity, Noise and/or ERC flows.
  • Deep understanding and experience of signoff aspects in STA for timing closure (OCV, constraints, parasitics), LVS, Static Power Analysis or Signal integrity analysis (Noise, SI-crosstalk).
  • Familiar with digital custom circuit transistor-level designs and topologies including dynamic circuit techniques and memories as well as SPICE models and netlists.
  • Desire to deep-dive into timing paths, perform QOR difference analysis and identify key issues.
  • Expertise with Linux environments and basic shell scripting.
  • Expertise is a must in 1 or more scripting languages such as Python, Perl and/or Tcl.
  • Knowledge in standard-cell liberty format syntax and digital circuit device-level SPICE modelling.
  • Knowledge in standard formats from 1 or more of transistor-level netlist, standard parasitic formats and/or SDC constraints.- EDA tool Tcl API coding.
  • Experience with advanced programming data structures.

Nice to Have

  • 1+ years of experience in one or more of the following: Cadence Virtuoso and/or SKILL coding.
  • Leading/Mentoring junior team members or prior interns.
  • Machine-learning/AI methods to solve complex problems dealing with automation of circuit design to aid in performance and power improvement.
  • Timing and power ECO techniques and implementation.

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Intel

Malaysia, Penang

Specialisation
Salary range
₹5-12 LPA to ₹35-60 LPA
Open roles at Intel
712 positions
Job ID
/job/Malaysia-Penang/E-Core-CPU-Design-Automation-Engineer_JR0280488

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