CPU Power Optimization Engineer

About This Role

• Do Something Wonderful! Intel creates world-changing technology that improves the lives of every person on the planet.
• Join us as we continue to innovate in high‑performance, low‑power CPU design.
• Who We Are Our CPU design organization delivers cutting-edge microprocessors with industry‑leading performance per watt.
• We build CPUs for desktops, servers, laptops, and emerging product families, consistently pushing IPC and power efficiency forward.
• Who You Are In this role on the Silicon Engineering Group, you will focus on power analysis and low‑power optimization for Intel CPUs .
• You will partner closely with design and architecture teams to drive solutions that elevate power efficiency and advance our product leadership.
• Your responsibilities will include, but not limited to: Drive power optimization efforts across architecture and RTL Identify opportunities to reduce dynamic and leakage power Propose and guide implementation of low‑power RTL changes Conduct feature‑ and workload‑based power analysis Close gaps between measured and targeted power on CPUs in development Develop and enhance power analysis and optimization methodologies Collaborate with architecture and RTL owners to deliver measurable results Provide recommendations for future CPU power architecture Qualifications: You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position.
• Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
• Minimum Qualifications and Experience: The candidate must have a Bachelor's degree in electrical/computer engineering, computer science or related field with 4+ years of experience.
• Or a Master's degree in the same fields with 3+ years of experience or a PhD in in the same fields with 1+ years of experience.
• Your experience described above must be in the following: Low-power CPU design Dynamic and leakage power estimation and reduction at architecture, RTL, block synthesis, or circuit level RTL design and RTL-level power optimization strategies Preferred Qualifications Proficiency with industry‑standard power estimation tools Scripting/automation skills Good understanding of CPU architecture and SoC‑level power behavior Experience driving RTL-level power optimization in collaboration with design teams Familiarity with Intel CPU architectures (strong plus) Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Texas, Austin Additional Locations: US, Oregon, Hillsboro Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.
• It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
• Find out more about the benefits of working at Intel .
• Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
• Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
• Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.