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About This Role
- Join us as a CPU DFD (Design-For-Debug) Validation Engineer and play a pivotal role in shaping the future of next generation of Intel CPU.
- In this role, you will ensure the reliability and functionality of cutting-edge CPUs by verifying DFD logic designs against specifications, and will develop various debug solutions in the form of software to support in-house post-silicon validation and external customers.
- This is a unique opportunity to collaborate with industry-leading architects, designers, and engineers to refine and advance Intel's CPU microarchitecture.
- Key Responsibilities Develop comprehensive DFD verification plans, test benches, and environments to achieve full coverage of DFD functionality against CPU microarchitecture specifications.
- Define and execute verification plans, run system simulation/emulation/FPGA models, analyze power and timing, and uncover bugs in the design.
- Develop software solution to support in-house post-silicon validation activities and external customers, and provide necessary post-silicon debug support as needed to internal validation/manufacturing and external customers Replicate, root cause, and debug issues in both pre-silicon and post-silicon environments, implementing corrective actions as needed.
- Collaborate with CPU architects, RTL developers, and physical design teams to ensure DFD usage models are viable for post-silicon debug usages Document detailed test plans and lead technical reviews with design and architecture teams.
- Maintain and improve existing functional verification infrastructure and methodologies.
- Contribute to the definition and development of innovative DFD architecture/microarchitecture features within the CPU design process.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience with a Bachelor's degree / Master's degree, or PhD graduate.
- Proficiency in SystemVerilog and UVM for pre-silicon verification.
- Strong scripting and programming skills in languages, particularly Python, Perl and C/C++.
- Robust understanding of CPU architecture and microarchitecture fundamentals.
- Proficiency in SystemVerilog and UVM, and with experience debugging any DFx issue in pre-silicon environment.
- Strong problem-solving and analytical skills with a creative approach to debugging and resolving issues.
- Effective communication and collaboration skills to work cohesively in a dynamic, fast-paced environment.
- Self-motivated individual with a passion for innovation and continuous learning.
- Preferred Qualifications Proven expertise/knowledge in TAP (Test Access Port).
- Prior knowledge in ASIC or FPGA design verification, particularly with x86 CPU designs.
- Prior knowledge in the use of emulation/FPGA for software/application prototyping.
Sourced directly from Intel’s career page
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652 positions
Job ID
/job/Malaysia-Penang/CPU-DFD-Validation-Engineer_JR0284862
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