Senior ASIC Verification Engineer

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Join us to help build the next generation of AI hardware solutions.
You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads.
With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact.
We are intentional, fast adopters of AI as a working tool.
We bring modern AI assistants and automation into every part of the verification flow — planning, stimulus and checker development, coverage analysis, debug and more — and we look to our senior verification engineers to help steer that evolution.
If you are energized by defining things that have never existed before, value rigorous thinking, and want real scope and short feedback loops - you'll feel right at home here.
This is a senior, hands-on role with broad technical influence.
You will own verification for meaningful parts of the chip — complex IPs and subsystems — building the environments that take them to sign-off, with room to influence the methodologies and working flows we adopt as a team.

Own verification strategy and execution for complex AI acceleration IPs and subsystems, grounded in deep understanding of the algorithms and microarchitecture under test.
Build verification environments, define verification plans, and drive coverage closure to sign-off.
Provide technical leadership and mentorship, and help shape the team's verification methodology and working flows, reviewing plans, environments, and results along the way.
Champion and advance the team's use of AI tools across the verification flow, finding where they add real leverage and helping the team adopt them well Collaborate closely with architects, designers, DFT, and emulation/bring-up teams to ensure correctness from block to system level.

B.Sc. in Electrical Engineering, Computer Engineering, or equivalent. 6+ years of hands-on functional verification experience, with a strong record of taking complex IPs/subsystems to sign-off.
Deep expertise in SystemVerilog/UVM, constrained-random and coverage-driven verification, and verification methodology and planning.
Strong intuition for working with AI tools and real interest in using them to advance the verification flow.
Demonstrated technical leadership: owning verification strategy, mentoring engineers, and driving decisions across teams.
Advantage Verification experience with accelerators, datapath, or compute-heavy IPs for AI/ML Strong familiarity with the broader development cycle, including design, DFT, and bring-up.

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