Opens intel.wd1.myworkdayjobs.com in a new tab
About This Role
- Develop and maintain RTL designs using Verilog/SystemVerilog for FPGA and ASIC solutions and perform functional simulation and verification to ensure the designs meet functional and performance specifications.
- Debug and resolve design and simulation issues, collaborate closely with architects, verification engineers, and system teams to clarify requirements, and support design integration, bring-up, and issue resolution.
- Ensure high design quality by following coding standards and maintaining proper technical documentation.
Requirements
- are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Requirements
- 5+ years of experience in RTL/Logic design on FPGA IP blocks using Verilog or SystemVerilog RTL coding.
Nice to Have
- Experience with Packet Based Protocols such as PCIe, USB, SPI, I2C and etc is an advantage.
- Experience in agentic AI is an advantage.
- Demonstrable experience in logic design and writing RTL in Verilog or SystemVerilog.
- Familiarity with a range of internal and 3rd-party logic design tools.
- Strong analytical ability, problem solving and communication skills.
- Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates.
- Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues.
- Strong communication and teamwork still.
- Ability to work independently and at various levels of abstraction.
- Ability to lead a team of designer.
- Knowledge in FPGA design and debug with FPGA tools like Quartus/Vivado will be an added advantage.
- Knowledge on embedded SW which using NIOS or ARM processor is an added advantage.
- Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
Opens intel.wd1.myworkdayjobs.com in a new tab
Specialisation
Salary range
₹4-9 LPA to ₹32-55 LPA
Open roles at Intel
712 positions
Job ID
/job/Malaysia-Penang/ASIC-FPGA-Design-Engineer_JR0280623
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — free
