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About This Role
- We are looking for a highly skilled Arithmetic Formal Verification Engineer to join our silicon design team.
- This role focuses on the formal verification of complex arithmetic hardware blocks, including fixed-point and floating-point datapaths.
- You will play a critical role in ensuring the mathematical correctness and corner-case robustness of arithmetic-intensive designs used in next-generation compute architectures.
- Key Responsibilities: Develop and execute formal verification strategies specifically targeting arithmetic logic units (ALUs), floating-point units (FPUs), dividers, multipliers, and custom math blocks.
- Develop formal verification testbenches and properties for arithmetic hardware designs.
- Collaborate with RTL designers to understand microarchitectural details and identify verification targets.
- Write and debug formal arithmetic specifications.
- Use formal tools (e.g., JasperGold, VC Formal, OneSpin) to prove correctness or find corner-case bugs.
- Analyze counterexamples and work with design teams to resolve issues.
- Contribute to the development of verification methodologies and best practices.
- Document verification plans, results, and coverage metrics.
Requirements
- You must possess a B.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ years of experience listed below; OR a M.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 4+ years of experience listed below; OR a PhD in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ months of experience listed below.
- The experience must include the following areas: • Strong understanding of digital design fundamentals, especially arithmetic circuits (e.g., adders, multipliers, dividers, floating-point units). • Hands on experience with industry standard formal verification tools such as JasperGold, Questa Formal, VC Formal. • Experience with formal abstractions and other complexity reduction techniques. • Experience with a hardware modeling language, such as Verilog, VHDL, or SystemVerilog and industry standard logic simulation tools. • Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis.
Nice to Have
- Knowledge of arithmetic computational formats. • Knowledge of theorem proving, model checking, or SAT/SMT solvers. • Knowledge of Intel Architecture ISA and system architecture, x86 assembly language. • Experience working in large-scale SoC or IP development environments. • Computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management. • Post-silicon debug and analysis.
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Salary range
₹5-12 LPA to ₹40-70 LPA
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Job ID
/job/Malaysia-Penang/Arithmetic-Formal-Verification-Engineer_JR0285441
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