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About This Role
- Drives end-to-end development for substrate design from concept through tape out and implements physical layout and routing of the package design.
- Performs substrate fit and routing studies to establish design, performance, and cost tradeoffs.
- Works closely with silicon and hardware teams to optimize silicon-package-board performance and pinout.
- Defines substrate design rules, conducts internal and external reviews, analyzes data, and resolves DRCs to optimize package design.
- Completes documentation and collateral into the product lifecycle management system of record.
- Required Skills and Experience: Self-motivated engineer who has strong technical background in design and electrical analysis.
- Solid background in semiconductor fabrication and packaging Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions. - Ability to work independently and at various levels of abstraction Strong organization, time management, and communication skills, self-motivated.
- Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.
- Experience in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP, Concept HDL, Sigrity), and/or Mentor Xpedition platform tools (PCB Layout/XPD, Designer, Hyperlynx).
- Experience and knowledge with assembly process, test and characterization techniques preferred Qualifications: Ph.D./master’s in electrical engineering/ chemical engineering/ mechanical engineering or Material Science. 10+ years and in-depth knowledge/background in Package, PCB design, or IC digital design.
Benefits
- We offer a total compensation package that ranks among the best in the industry.
- It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.
- Find out more about the benefits of working at Intel .
- Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations.
- Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
- Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Sourced directly from Intel’s career page
Your application goes straight to Intel.
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Specialisation
Salary range
₹4-10 LPA to ₹40-75 LPA
Open roles at Intel
95 positions
Job ID
/job/US-Arizona-Phoenix/ADCE-Packaging-Design-Architect_JR0284396
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