Opens cadence.wd1.myworkdayjobs.com in a new tab
What You'll Do
- Serve as the primary technical contact for post-silicon bring-up and debug of Memory IP subsystems.
- Support customer SOC and system integration, including ATE deployment and production ramp.
- Collaborate with internal teams (Analog/Digital Design, DV, Program Management) to resolve technical issues.
- Participate in silicon evaluations, demos, and onsite bring-up for tier-one customers.
- Travel requirements : Approximately 10% Provide integration training and recommendations to customers.
- Analyze and resolve complex subsystem application or implementation issues.
- Contribute to documentation, checklists, and collateral improvements for enhanced customer experience.
- Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables.
- Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.
- Required Qualifications M.S. in Electrical/Computer Engineering (or similar) with 7+ years of experience, or Ph.D. with 5+ years of relevant experience.
- Strong background in post-silicon bring-up and debug.
- Experience working with DDR5/4/3, LPDDR5/4/3, HBM3/4, GDDR6/7 or similar IPs.
- Hands-on experience with lab equipment for reproducing and debugging customer issues.
- Ability to read schematics and participate in SI/PI reviews for customer board/package implementation.
- Excellent problem-solving, presentation, and communication skills.
- Preferred / Optional Skills Exposure to STA and RTL flows would be beneficial.
- Familiarity with advanced mixed-signal verification and system simulation tools is a plus.
- Why Join Us? Work on cutting-edge memory technologies impacting next-generation systems.
- Collaborate with global teams and industry-leading customers.
- Competitive compensation and benefits package.
- Opportunities for career growth and technical leadership.
- The annual salary range for California is $154,000 to $286,000.
- You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
- Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
- Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
- Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
- We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
Your application goes straight to Cadence Design Systems.
Opens cadence.wd1.myworkdayjobs.com in a new tab
Specialisation
Open roles at Cadence Design Systems
658 positions
Job ID
/job/SAN-JOSE/Sr-Principal-Product-Engineer---Memory-IP_R52037
Get matched to roles like this
Upload your resume once. We’ll notify you when matching roles open up.
Join talent pool — freeSimilar Other roles
Samsung Semiconductor
Staff Technical Program Manager
San Jose, California, United States|Other
Samsung Semiconductor
Associate, Executive Administration
San Jose, California, United States|Other
Micron Technology
STAFF ENGINEER GFAC SASIA - ELECTRICAL
Fab 10A, Singapore|Other
Micron Technology
TEST HBM DATA ANALYST
Taichung - MTB, Taiwan|Other