Design Engineer I

What You'll Do

• Design RTL for high-speed Ethernet MAC, PCS, and FEC IP cores across multi-rate, multi-port architectures (10Gb through 1.6Tb) Collaborate daily with design, verification, and back-end engineers — all co-located in Cork Learn and apply digital design best practices: synthesis, timing closure, and configurable IP delivery Job Qualifications: Degree in Electronic/Electrical or Computer Engineering (Bachelor's minimum) Solid understanding of digital design fundamentals — RTL, state machines, clocking, timing Exposure to Verilog or SystemVerilog (academic or industry) Strong analytical and problem-solving skills Ability to work effectively in a team Additional Skills/Preferences: Any exposure to Ethernet standards or high-speed networking Familiarity with simulation/debug tools (Xcelium, VCS, ModelSim) Experience with synthesis or FPGA implementation Awareness of FEC or signal integrity concepts Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• We’re doing work that matters.
• Help us solve what others can’t.