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What You'll Do
- the following: · Researching tools, languages, methodologies and prototype processes to enhance product verification as well as to demonstrate product quality. · Updating, enhancing, maintaining, and supporting existing system level UVM test environments for memory model products. · Supporting product (IP Library) regression, OS compliance, process automation, and product release preparation as needed.
- Job Responsibilities & Skills: [Principal Verification Engineer (T4) ] · Candidate must be an Electrical, Electronics or Computer Science Engineer with expert understanding of HDLs and HVLs such as Verilog and SystemVerilog. · Solid experience in simulation/emulation using these languages.
- He/ she should have expert working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/verification problems using these tools. · Deep experience with UVM, SystemVerilog, and C++. · Must have solid, deep experience on multiple protocols such as UFS Unipro and MPHY, SDRAM, Ethernet, PCIe, USB3/4, MIPI etc · Experience with Functional Verification of complex digital systems, e.g.
- SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. · Experience with Functional Verification of complex protocol-based blocks—e.g.
- UFS / Unipro / MPHY verification—with a Hardware Verification Language (HVL) like SystemVerilog. · Experience designing and implementing complex functional verification environments is required. · Experience in process automation with scripting is required.
- Behavioral skills required. · Possess very strong English verbal and written skills. · Ability to establish close, collaborative working relationships with team colleagues, peers, customers, vendors, and management. · Likewise, the ability to execute with strong individual and independent R&D skills. · Motivation and capacity to mentor less experienced engineers and to participate in cross-functional projects. · Explore what’s possible to complete a committed job while maintaining high product quality. · Work effectively across functions and geographies. · Participate in team processes; evaluate and recommend process improvements.
- Strongly recommended: · Verification experience using Cadence simulation and/or emulation products is highly desired. · Experience in memory sub-system or controller verification and operation is strongly recommended.
- We’re doing work that matters.
- Help us solve what others can’t.
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Specialisation
Salary range
₹5-12 LPA to ₹40-70 LPA
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658 positions
Job ID
/job/SHANGHAI/Principal-Verification-Engineer_R53489-1
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