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What You'll Do
- Testbench development, test creation, and execution Debugging simulation failures and protocol issues Functional, code, and assertion coverage closure Collaboration with design, architecture, and validation teams Support regression, reviews, and verification sign-off Mandatory Skills: 7-12 years of experience in IP / SoC Verification Strong hands-on experience with SystemVerilog & UVM Experience with one or more high-speed protocols: Good understanding of SoC fundamentals Strong debugging and problem-solving skills Good to Have Low-power verification knowledge ( UPF/ CPF) Scripting skills ( Python / Perl / Shell) EDUCATION: MS in Electrical/Electronics/Computer Engineering with 7+ year experience or BE/BTech in Electrical/Computer/Electronics Engineering.
- Behavioral skills required: Must possess strong written, verbal and presentation skills.
- Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
- Ability to establish a close working relationship with both customer peers and management.
- Explore what’s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity We’re doing work that matters.
- Help us solve what others can’t.
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Specialisation
Open roles at Cadence Design Systems
676 positions
Job ID
/job/NOIDA/Principal-Product-Validation-Engineer_R54405
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