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What You'll Do
- Protocol & Physical Layer: Demonstrate a strong understanding of DDR, LPDDR and GDDR implementations.
- Primary Technical Liaison: Act as the main technical contact for debugging customer silicon issues, both for systems and ATE Lab Equipment Proficiency: Demonstrate hands-on experience with oscilloscopes, BERTs, protocol exercisers, and analyzers.
- Signal Integrity (SI) and Power Integrity (PI): Understand SI and PI requirements for the IP and assist in diagnosing related hardware issues.
- Onsite Support: Travel to customer sites (about 10% of the time) for bringup and debug of silicon issues.
- Technical Issue Management: Own support cases filed by the customer on SFDC.Use tools such as Sherlock and JIRA to document and coordinate issue debugging.
- AI Incorporation: Leverage AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables.
- Apply AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets.
- Required Skills & Qualifications M.S.
- Electrical/Computer Engineering (or similar degree) and 10 + years of experience or PhD and 5+ Years of relevant experience Experience working with Memory PHY, Memory Controller and DRAM Experience using advanced mixed signal verification, and system simulation tools.
- Strong debug and problem-solving skills.
- Strong background in supporting Post Silicon bringup and debug.
- Familiarity with advanced technology nodes (7nm and below) is a plus.
- Strong presentation and communication skills required.
- Experience with lab equipment to reproduce customer failures in the lab.
- Familiarity with SI/PI analysis concepts and able to diagnose hardware issues We’re doing work that matters.
- Help us solve what others can’t.
Sourced directly from Cadence Design Systems’s career page
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Specialisation
Open roles at Cadence Design Systems
658 positions
Job ID
/job/SHANGHAI/Sr-Principal-Product-Engineer-DDR-IP-_R52751
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