Principal Product Engineer

What You'll Do

• Drive, validate, and promote an end-to-end solution for system design implementation flows spanning 3D IC, heterogeneous integration and advanced packaging.
• Partner with leading semiconductor customers to understand complex system co-design challenges and translate them into clear product specifications.
• Produce high-quality Product Requirement Specifications (PRS), technical use cases, and support R&D throughout product development.
• Collaborate cross-functionally with R&D, Product Management, Field teams, Technical Publications and Product Validation to deliver robust, customer-ready capabilities.
• Create and deliver demonstration collateral, application workflows, and enablement materials to accelerate customer and field adoption.
• Troubleshoot design-flow issues, provide technical guidance and workarounds, and drive bug/enhancement prioritization.
• Support product launches, customer engagements, and industry events.
• Own deliverables from definition through customer deployment with a strong focus on execution and accountability.
• Job Qualifications: BS in Electrical Engineering, Electronics, or a related technical field.
• Strong experience in semiconductor design, physical implementation, advanced packaging, or EDA product engineering.
• Strong hands-on knowledge of the Cadence Virtuoso platform and associated custom IC design flows. 10+ years of relevant experience, or equivalent demonstrated expertise.
• Proven ability to work independently, prioritize effectively, and take responsibility for technical deliverables.
• Strong verbal and written communication skills, with the ability to collaborate effectively across global and multicultural teams, and across functions.
• Highly motivated by the rapidly evolving landscape of 3DIC, heterogeneous integration, and advanced packaging technologies, with a passion for driving innovation in next-generation semiconductor solutions.
• Additional Skills/Preferences: Experience with software product definition, validation, or technical marketing activities.
• Experience with co-design flows around 3D IC, heterogeneous integration, silicon-package-board integration.
• Knowledge of Cadence Allegro Package Designer Plus (APD+) and package implementation methodologies.
• Knowledge of Cadence Virtuoso SKILL language or any other interpreted language.
• Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• The annual salary range for California is $140,000 to $260,000.
• You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
• Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
• Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
• Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
• We’re doing work that matters.
• Help us solve what others can’t.