Principal IC Digital Implementation AE

Opens cadence.wd1.myworkdayjobs.com in a new tab

What You'll Do

  • Be part of team of Application Engineers providing technical support to Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing/power signoff Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules Collaborate with team to conduct technical presentations and product demonstrations Drive technical evaluations/benchmarks to success Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements Drive adoption and proliferation of Cadence tools and technologies Provide guidance to the team to amend & augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements Job Requirements Minimum 10+ years of industry Physical Design experience BS degree Computer Science/Engineering, Electrical, Engineering, or related field Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required Prior experience with IC digital implementation flows and backend EDA tools including Place and Route, IR Drop, backend design timing and power closure Experience with advanced nodes 10nm and below Experience in scripting languages such as Tcl/Perl/Python is a must Strong customer-facing communication and problem-solving skills Strong personal drive for continuous learning and expanding professional skill sets Strong verbal, written, and customer communication skills Preferred MS degree Computer Science/Engineering, Electrical, Engineering, or related field Prior experience with IC digital implementation flows and font-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking Prior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, Voltus or ICC, ICC2, DC or Primetime is highly desired Experience with advanced nodes 5nm and below The annual salary range for California is $123,200 to $228,800.
  • You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
  • Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.
  • Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.
  • Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
  • We’re doing work that matters.
  • Help us solve what others can’t.

Sourced directly from Cadence Design Systems’s career page

Your application goes straight to Cadence Design Systems.

Specialisation
Open roles at Cadence Design Systems
658 positions
Job ID
/job/SAN-JOSE/Principal-Application-Engineer_R53834

Get matched to roles like this

Upload your resume once. We’ll notify you when matching roles open up.

Join talent pool — free

Similar Other roles