Principal Design Engineer - ( Synthesis/LEC/CLP )

What You'll Do

• Drive methodology improvements and best-practice development across Synthesis, LEC, CLP and ECO flows.
• Own end-to-end LEC sign-off across multiple design blocks including debug of NEQs, aborts.
• Drive Physical synthesis closure on complex blocks including constraint development and PPA closure.
• CLP sign-off for low power intent designs: level shifter, retention, isolation, PSO strategy architecture, supply set/domain conflict resolution.
• Own technical documentation, status tracking, and write-ups across active blocks.
• Required Skills 8–12 years of hands-on ASIC/SoC design experience with strong depth in Synthesis (Genus), LEC (Conformal), and Low Power.
• Proven experience across multi-corner, multi-mode sign-off considerations Strong scripting ability in TCL, Python, PERL etc.
• Deep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, DFT.
• Excellent written and verbal communication skills; comfortable owning technical documentation and cross-team discussions Proven track record and experience working in a fast-paced environment.
• Preferred Experience with physically aware synthesis flows Regards K Madhu Prasad kmadhup@cadence.com We’re doing work that matters.
• Help us solve what others can’t.