Principal Product Engineer – High-Speed IP UCIE

What You'll Do

• Act as the primary product engineering owner for UCIE die-to-die subsystems at the customer level Lead customer engagements, drive technical discussions, design reviews, and deployment strategy Own and drive resolution of complex subsystem integration and implementation issues Lead SoC integration reviews covering PHY and controller subsystems Provide technical leadership for RTL, gate-level simulations, and timing closure strategies Define and drive improvements to integration methodologies, checklists, and customer collateral Lead post-silicon bring-up and debug activities, ensuring successful customer deployment Collaborate cross-functionally with R&D, validation, and applications teams to deliver product readiness Drive continuous improvement in customer experience, turnaround time, and engineering quality Mentor junior engineers and provide technical guidance across projects and teams Leverage AI tools to improve debug efficiency, data analysis, and decision-making Position Requirements Strong experience with high-speed interface IP Deep understanding of RTL design, gate-level verification, and simulation methodologies Experience with synthesis, STA, and timing closure; backend knowledge is a plus Familiarity with DFT methodologies, test flows, and system validation approaches Skills & Qualifications [Required] Bachelor’s in electrical engineering, Computer Engineering, or related field with 7+ years of experience, or Master’s with 5+ years, or PhD with relevant experience Proven ability to solve complex technical problems and drive root cause to closure Experience leading cross-functional technical efforts across design, validation, and customer teams Strong communication skills with ability to influence customer and internal stakeholders Experience managing multiple priorities, escalations, and technical reviews Demonstrated ability to represent the organization in customer-facing technical roles Strong ownership mindset and ability to drive deliverables independently [Preferred] Experience with memory and/or high-speed communication interfaces (DDR, LPDDR, PCIe, Ethernet, UCIe, USB) Understanding of analog/mixed-signal design practices Experience in customer-facing silicon debug and bring-up environments Familiarity with AI-assisted workflows and data-driven debug techniques We’re doing work that matters.
• Help us solve what others can’t.