Lead Design Engineer

What You'll Do

• Verification ownership of a feature from start to finish.
• Define and develop detailed test plans, execution, sign off Develop SystemVerilog/UVM testbench and infrastructure.
• Apply formal verification methodology for verification sign off and quality.
• Develop and apply novel verification techniques for verifying performance of designs.
• Collaborate with design team to understand the micro-architecture and pipeline.
• Position Requirements: Strong knowledge of computer architecture, especially processor pipeline and vector processing.
• Knowledge of DSP arithmetic functions.
• Exposure in hardware verification concepts such as assertions, scoreboard, coverage. knowledge in Verilog, SystemVerilog and UVM.
• Familiarity of AI in Design and DV is preferred Familiarity with performance modelling and verification including benchmarks.
• Understanding and basic proficiency in C or C++ Proficiency in any scripting language (Python or Perl preferred) Familiarity with source code control (Git/Perforce) Ability to work efficiently with remote teams in different time zones Ability to work successfully both independently and in a team environment Strong problem-solving skills, flexible, adaptable and proactive Strong communication skills MSEE, MSCE.
• MS and 2 years of working in a design or verification role We’re doing work that matters.
• Help us solve what others can’t.