Layout Design Engineer II (SerDes)

What You'll Do

• Perform custom transistor-level layout for high-speed SerDes blocks, including PLLs, Clock and Data Recovery (CDR), TX/RX analog front-ends, equalisers (CTLE/DFE), bandgap and bias circuits, and high-speed clock distribution networks.
• Partner closely with analog and mixed-signal circuit designers to understand performance requirements and optimise floorplanning, parasitic-sensitive routing, signal integrity, and matching.
• Support physical design implementation activities such as floorplanning, device placement, routing, shielding and isolation, power planning, and EM/IR-aware layout practices.
• Run and debug physical verification flows, including DRC, LVS, ERC, parasitic extraction, and post-layout verification support.
• Apply advanced layout techniques such as common-centroid structures, interdigitation, symmetry constraints, guard rings, dummy fill, and matching-aware routing.
• Optimise layouts for area, yield, performance, reliability, and manufacturability.
• Collaborate with cross-functional teams including Analog Design, Digital Implementation, Packaging, Signal Integrity, and Physical Verification.
• Job Qualifications: Essential (Must-have) Degree in Electronic Engineering, Microelectronics, Computer Engineering, or a related discipline, or equivalent industry experience.
• Hands-on experience with CMOS SERDES or high-speed I/O IC layout at the transistor level.
• Practical knowledge of custom layout methodologies and parasitic-aware design techniques.
• Ability to collaborate effectively with designers and project stakeholders across global teams.
• Strong problem-solving skills, clear communication, and a collaborative working style.
• Desirable (Nice-to-have) Experience with PHY GDS implementation, including PMA/PCS integration and clock/power distribution.
• Familiarity with ASIC design flows, hierarchical physical design strategies, and deep sub-micron technology challenges.
• Exposure to EM/IR, low-power design considerations, crosstalk analysis, physical verification, and DFM.
• Experience contributing to tape-outs on advanced technology nodes (e.g. 16nm, 10nm, 7nm, 5nm, or 3nm).
• Scripting or automation experience using Tcl, Perl, or Python.
• Prior use of Cadence tools or collaboration with EDA R&D teams (e.g.
• Additional Information: Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization.
• We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.
• We’re doing work that matters.
• Help us solve what others can’t.