Lead Design Engineer

What You'll Do

• Key contributor and senior technical engineer in the IP frontend design team, especially on high-performance Consumer PHYs including eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA, etc.
• Drive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process Understanding of synthesis, constraint generation, power management and DFT Understanding of low-power designs and features (power islands, state retention, isolation, etc.) Work with digital verification team to specify coverage points, testing strategy, corner conditions, stimulus creation and FPGA/Palladium testing Partner closely with Project Management Office to collaborate with various skill groups in Nanjing and multiple worldwide geographies to complete the IP deliverables with high quality, including Analog, Layout, Backend, Firmware, Lab Bring-up/Validation, Pre/Post-Silicon Product Engineering Work with wider engineering and IP delivery/release teams to develop and use infrastructure to integrate IPs into subsystems and QA for customer releases Position Requirements: MS / BS in Electrical/Computer Engineering or related degree. 5+ years of relative industry working experience. 3+ years of experience in ASIC design role for delivering advanced IP and/or ASIC/SOC products.
• Deep knowledge of best practices and flows in Design Architecture, RTL design/verification and ASIC end-to-end methodology.
• Knowledge of one or more industry serial standards, such as USB, DP, PCIe, Ethernet, etc.
• Understanding basics of Analog Mixed-Signal, SI/PI, Post-Silicon Validation, and system view of physical interface IPs and their typical applications.
• One Team mentality with a passion to innovate and can-do attitude.
• Strong cross-functional communication skills in both English and Mandarin.
• Self-starter and highly motivated.
• Qualifications as Plus Direct experience of high-speed serial interface link IPs in advanced technology nodes.
• Knowledge of multiple programming languages, SystemVerilog, Python, C/C++, etc.
• Knowledge of embedded microcontroller or DSP usage and FW.
• Experience with various Cadence ASIC design tools.
• We’re doing work that matters.
• Help us solve what others can’t.