Design Engineering Architect

Overview

• At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
• Candidate will be responsible for efficiently driving various customer engagements for multiple IP product lines with customer-specific feature set Solid technical background in IP design and verification.
• Experience working in direct customer facing role.
• Candidate’s background should include a minimum of 18-20 years of experience in CMOS SerDes, ADC, or high-speed I/O IC design and development Working knowledge of a set of common SerDes standards and their electrical Must have a thorough understanding of jitter and signal equalization techniques Design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; Bias and Bandgap; and Voltage Regulators Proficient Design Experience with ADC Designs and Architectures.
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment Experience and understanding of technical requirements preferably with working knowledge of multiple other IP product lines and related areas Strong technical communication skills Capable of understanding multiple issues/program directions and communicating their impact at the overall customer engagement level Can independently resolve a wide range of issues in creative ways on a regular basis We’re doing work that matters.
• Help us solve what others can’t.